1. Field of the Invention
This invention relates to a semiconductor device advantageous to miniaturization and a method of manufacturing the same.
2. Description of the Prior Art
There occurs the problem that, with development of miniaturization of MISFET (Metal Insulation Silicon Field Effect Transistor), the punch-through is apt to take place between the drain and source by the short-channel effect. With a view to solving this problem, a LDD (lightly doped drain) structure has been conventionally devised. Namely, this LDD structure is a structure having a lightly doped drain-source. When attention is drawn to, e.g., an n-channel MOSFET, the field oxide film sides of the drain region and the source region are caused to be an n.sup.+ layer and the channel formation layer sides thereof are caused to be an n.sup.- layer to set the impurity concentration at the channel side end portions of the drain and the source to a relatively lower value to thereby relax the drain electric field, to improve the withstand voltage, and to prevent the punch-through(penetration) between the drain and the source by the short-channel effect.
FIGS. 1A-1D show particularly a method of forming diffused layers serving as source and drain regions of a typical manufacturing process of a MOSFET having such LDD structure and its LDD elemental device structure.
In these figures, ion implantation for well is first implemented into a silicon substrate 701 thereafter to carry out extending diffusion of the implanted impurity to thereby form a well to subsequently carry out an ion implantation for prevention of parasitic channel. Thereafter, selective oxidation is implemented onto the substrate 701 surface to form field oxide film 702 to carry out isolation of the elemental device region (hereinafter simply referred to as the device region) from others. Then, a gate electrode material oxide film by thermal oxidation is formed on the entire surface of the region surrounded by the oxide film 702 on the substrate 701 to subsequently form a gate electrode material polycrystalline silicon (hereinafter polysilicon) film on the entire surface of the oxide film by using the LPCVD process so that its thickness reaches 2,000 angstroms. Thereafter, a mask of photoresist is formed on the polysilicon film serving as a gate electrode material by the optical lithography to implement patterning to the gate electrode material oxide film and the gate electrode material polysilicon film by using the RIE process thus to form a gate electrode comprised of a gate oxide film 703 and a polysilicon film 704 (FIG. 1A).
In the case where the MOSFET to be manufactured is a p-channel MOSFET, implantation of ions 705 of impurity BF.sub.2.sup.+ is then carried out under the condition of a low dose (about 1.times.10.sup.13 cm.sup.-2) and an acceleration voltage of about 30 KeV (FIG. 1B). In the figure, reference numeral 706 represents a low concentration ion implanted region which is to serve as a source formed by that ion implantation, and reference numeral 707 represents a low concentration ion implanted region which is to serve as a drain formed by that ion implantation.
Thereafter, a silicon oxide film is deposited on the substrate 701 entire surface by the LPCVD process so that its thickness reaches about 1000 angstroms to subsequently carry out the RIE process, thereby allowing oxide film portions 708, 709 in a side wall form to be left on the side surfaces of the gate electrode. Further, implantation of ions 705 of impurity BF.sub.2.sup.+ is in turn carried out ordinarily under the condition of a higher dose more than 1.times.10.sup.15 cm.sup.-2 and an acceleration voltage of about 30 KeV (FIG. 1C). Thus, a high concentration ion implanted region 710 is formed at the portion which is to serve as the source on the substrate 701, and a high concentration ion implanted region 711 is formed at the portion which is to serve as the drain on the substrate 701.
Then, the RTA (Rapid Thermal Annealing) process is carried out for 20 seconds at 1000.degree. C. Then, after activation of ion implanted impurity has been conducted, metal silicide films 714, 715 are formed on the surface portions of the respective ion implanted regions 710, 711 by the SALICIDE (Self Align Silicide) process to thereby carry out activation of impurity to form the source region comprised of a high concentration diffused layer 716 and a low concentration diffused layer 717 and the drain region comprised of a high concentration diffused layer 718 and a low concentration diffused layer 719. Thus, LDD structures (low concentration diffused layers 717, 719) shallow in depth which have a low carrier concentration in correspondence with a carrier concentration of the substrate 701 are formed on the both sides of the channel formation region below the gate oxide film 703 (FIG. 1D).
Meanwhile, although such LDD structure has an advantage of suppression of the short-channel effect as previously described, it has the problem that since the channel side portions of the drain and source are caused to have a low concentration, the resistance between the source and the drain increases by lowering of concentration, resulting in a lowered current drivability. For this reason, in the case where the short-channel effect is not so problem in relation to the power supply voltage specification, there were instances where such a LDD structure is not employed.
However, it is considered that the action of suppression of the short-channel effect by the LDD structure is very useful for miniaturization of MOSFET. In view of this, inventors conducted a simulation to study an optimum mode (structure, impurity profile, etc.) of this LDD structure. As a result, it is found that from the both points of view of suppression of the short-channel effect and assuring of a drivability, the construction in which a shallow diffused layer having high concentration which cannot be realized by optimizing the conventional method and a diffused layer required to have a certain depth when the salicide process is taken into consideration are provided is required.
To form the LDD structure as described above in practice, after a gate electrode has been formed on a silicon substrate via a gate oxide film, impurity ions are implanted at a low dose rate. Further, after an insulating film has been formed on a gate side wall, impurity ions such as arsenic are implanted at a high dose rate. By the above-mentioned process, a shallow diffusion layer of a low concentration can be formed near the gate, and a deep diffusion layer of a high concentration can be formed outside the shallow diffusion layer. Further, a saliside film is formed on the deep diffusion layer of a high concentration.
However, this method involves various problems as follows: In the LDD structure, although there exists such an effect as to suppress a short channel effect, since the channel side of the drain and source is low in concentration, the resistance between the source and the drain increases by that extent, so that a problem arises in that the current drive capability is lowered. Accordingly, there exists such a case that the LDD structure is not adopted, when the short channel effect is not important from the point of view of element reliability in relation to the supply voltage specifications.
In addition, in the prior art NMOS transistors, although the diffusion layer of the source and drain is formed by ion (e.g., arsenic) implantation, the maximum junction depth is 40 nm at its minimum, and it has been difficult to obtain the junction depth less than 40 nm. Furthermore, when the gate length is less than 0.17 .mu.m, since the short channel effect becomes prominent and further the threshold voltage Vth disperses, with the result that a serious problem arises in that the LSI characteristics fluctuate extremely large.
On the other hand, it is possible to form a shallow area of high concentration carriers, without forming the side wall insulating film on both sides of the gate. In this method, however, since the scaling rule cannot be applied to the contact resistance, in the indispensable saliside process, silicon is consumed at a composition ratio of silicon to metal contained in the metallic film formed on the substrate. Therefore, when the diffusion layer is formed shallow, the carrier concentration decreases at an interface between the metal siliside film and the substrate, so that the contact resistance increases and further the distance decreases from the electrode, through the interface of the source and drain diffusion layer regions and the source and drain diffusion layer regions, to the pn junction of the substrate. Consequently, leak current increases and further the depth of the diffusion layer (the degree of shallowness) is limited.
Further, in the conventional MOS transistors operative at room temperature, the minimum gate length obtainable was 70 nm (T. Hashimoto et al. "3V operation of 70 nm gate length MOSFET with new double punch through stopper structure", in Ext. Abs. of Ing. Conf. on Solid State Devices and Materials. pp 490 to 492, August 1992). In other words, it has been so far difficult from the technical point of view to from the MOSFET having a gate length less than 70 nm.
As described above, when MOSFET is miniaturized, although the LDD structure is suitable for suppression of the short channel effect, since the resistance between the source and the drain increases, there exists a problem in that the current drive capability deteriorates.